VLSI Design & Chip Architecture

About the Course

The VLSI Design & Chip Architecture Course by SkillDzire provides an in-depth understanding of semiconductor fundamentals, CMOS technology, front-end and back-end VLSI design, digital and analog circuit design, RTL coding, synthesis, STA, and verification methodologies. Learners gain practical exposure through EDA tools and real-world chip design projects.

Comprehensive VLSI front-end and back-end design training

Hands-on exposure to RTL design and verification

Master CMOS, ASIC, FPGA, and SoC design flows

Industry-recognized certification and placement guidance

Curriculum

Introduction to VLSI Systems

VLSI Evolution & Applications
Moore’s Law and Technology Scaling
Design Flow Overview
Types of ICs: ASIC, FPGA, SoC

Digital Design Fundamentals

Number Systems & Boolean Algebra
Logic Gates & Truth Tables
Combinational Circuits
Sequential Circuits
FSM Design (Mealy & Moore)
Timing Analysis, Setup/Hold Concepts

HDL: Verilog HDL

Syntax, Modules, Data Types
Combinational Design in Verilog
Sequential Design in Verilog
Testbenches and Simulation

HDL: SystemVerilog & UVM

SystemVerilog Features, Data Types, OOP
Constrained Random Verification
Assertions (SVA)
UVM Testbench Structure, TL Modeling

FPGA & ASIC Design Flow

FPGA Architecture & Resources
RTL to Bitstream: Synthesis, Implementation
ASIC Flow Overview
Design Constraints (SDC)
Technology Libraries & IP Cores

Synthesis & STA

Logic Synthesis Flow
Constraints, Optimization & Mapping
Multi-cycle & False Paths
Setup & Hold Analysis
Clock Skew and Jitter

Design for Testability (DFT)

Importance of Testing in VLSI
Scan Design, ATPG Concepts
Built-In Self-Test (BIST)
Boundary Scan (JTAG)
Fault Models & Coverage

EDA Tools & Workflows

RTL Simulation Tools
Synthesis Tools
Place and Route Tools
Layout Verification Tools
Power/IR Drop/Signal Integrity

Physical Design

Floorplanning & Partitioning
Placement & Clock Tree Synthesis (CTS)
Routing
- Global & Detailed
Parasitic Extraction
Timing Closure & ECO
Physical Verification
- DRC, LVS, Antenna Effects

Analog & Mixed-Signal VLSI

CMOS Analog Circuit Basics
Op-Amps, Comparators, Oscillators
ADC/DAC Architectures
Analog Layout Techniques

FPGA/ASIC Prototyping

FPGA Board Setup & Programming
Interfacing & Peripheral Integration
ASIC Tapeout Overview

Trends & Industry Practices

Low-Power & High-Speed Design Techniques
Design for Manufacturability (DFM)
Recent Trends, Careers

Hands-On Real-Time Exposure Tasks

Arithmetic Logic Unit (ALU) with Pipelined Design
8-bit RISC-V Based Simple Processor
Traffic Light Controller (Smart & Priority-Based)
Lift/Elevator Control System
Digital Currency Counter with Pulse Detection
Automatic Room Temperature Controller (Smart HVAC)
Washing Machine Controller FSM
Simple Synchronous FIFO with Low-Latency Design
Universal Asynchronous Receiver-Transmitter (UART) with Error Detection
High-Performance Pipelined Processor with Hazard Mitigation

Download Full Curriculum (PDF)

Projects You Will Work On

4-bit ALU Design

Design and simulate an Arithmetic Logic Unit using Verilog and perform timing analysis.

8-bit Microprocessor Design

Develop and verify a simple microprocessor with control and data paths in HDL.

ASIC Flow Implementation

Work on synthesis, placement, routing, and timing closure using industrial EDA tools.